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256MB - 32Mx64 DDR SDRAM UNBUFFERED
FEATURES
DDR200, DDR266 and DDR333 * JEDEC design specifications Double-data-rate architecture Industrial temperature Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power supply: 2.5V 0.20V Industrial temperature options Standard 200 pin SO-DIMM package * Package height option: D4: 31.75mm (1.25")
NOTE: Consult factory for availability of: * Lead-free products * Vendor source control option * Industrial temperature option
W3EG6432S-D4
PRELIMINARY*
DESCRIPTION
The W3EG6432S is a 32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of eight 32Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to change without notice.
OPERATING FREQUENCIES
DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-3-3 DDR200 @CL=2 100MHz 2-2-2
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PIN CONFIGURATION
PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SYMBOL PIN# VREF 51 VREF 52 53 VSS VSS 54 DQ0 55 DQ4 56 DQ1 57 DQ5 58 VCC 59 VCC 60 DQS0 61 DQM0 62 DQ2 63 DQ6 64 65 VSS VSS 66 DQ3 67 DQ7 68 DQ8 69 DQ12 70 VCC 71 VCC 72 DQ9 73 DQ13 74 DQS1 75 DQM1 76 VSS 77 VSS 78 DQ10 79 DQ14 80 DQ11 81 DQ15 82 VCC 83 VCC 84 CK0 85 VCC 86 CK0# 87 88 VSS VSS 89 VSS 90 DQ16 91 DQ20 92 DQ17 93 DQ21 94 VCC 95 VCC 96 DQS2 97 DQM2 98 DQ18 99 DQ22 100 SYMBOL PIN# VSS 101 VSS 102 DQ19 103 DQ23 104 DQ24 105 DQ28 106 VCC 107 VCC 108 DQ25 109 DQ29 110 DQS3 111 DQM3 112 VSS 113 VSS 114 DQ26 115 DQ30 116 DQ27 117 DQ31 118 VCC 119 VCC 120 NC 121 NC 122 NC 123 NC 124 VSS 125 VSS 126 NC 127 NC 128 NC 129 NC 130 VCC 131 132 VCC NC 133 NC 134 NC 135 NC 136 VSS 137 VSS 138 NC 139 VSS 140 NC 141 VCC 142 VCC 143 VCC 144 NC 145 CKE0 146 NC 147 NC 148 A12 149 A11 150 SYMBOL PIN# A9 151 A8 152 VSS 153 VSS 154 A7 155 A6 156 A5 157 A4 158 A3 159 A2 160 A1 161 A0 162 VCC 163 VCC 164 A10/AP 165 BA1 166 BA0 167 RAS# 168 WE# 169 CAS# 170 CS0# 171 NC 172 NC 173 NC 174 VSS 175 VSS 176 DQ32 177 DQ36 178 DQ33 179 DQ37 180 VCC 181 VCC 182 DQS4 183 DQM4 184 DQ34 185 DQ38 186 VSS 187 VSS 188 DQ35 189 DQ39 190 DQ40 191 DQ44 192 VCC 193 VCC 194 DQ41 195 DQ45 196 DQS5 197 DQM5 198 VSS 199 VSS 200 SYMBOL DQ42 DQ46 DQ43 DQ47 VCC VCC VCC CK1# VSS CK1 VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DQM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DQM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 VCCID
NC
W3EG6432S-D4
PRELIMINARY
PIN NAMES
A0-A12 BA0-BA1 DQ0-DQ63 DQS0-DQS7 CK0, CK1 CK0#, CK1# CKE0 CS0# RAS# CAS# WE# DQM0-DQM7 VCC VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect
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FUNCTIONAL BLOCK DIAGRAM
CS0# DQS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS7 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 120 BA0, BA1 A0-A12 RAS# CAS# CKE0 WE# BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs WE#: DDR SDRAMs CK1 CK1# 120 CK0 CK0# DM CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS6 DQM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS5 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS4 DQM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
W3EG6432S-D4
PRELIMINARY
DDR SDRAM X 4
DDR SDRAM X 4
SERIAL PD SCL WP SDA A0 A1 A2 SA0 SA1 SA2
VCCSPD
VCC
VREF
SPD DDR SDRAMs DDR SDRAMs DDR SDRAMs
VSS
NOTE: All resistor values are 22 ohms unless otherwise specified
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
W3EG6432S-D4
PRELIMINARY
Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS
Value -0.5 to 3.6 -1.0 to 3.6 -55 to +150 8 50
Units V V C W mA
DC CHARACTERISTICS
0C TA 70C, VCC = 2.5V 0.2V Symbol VCC VCCQ VREF VTT VIH VIL VOH VOL Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Min 2.3 2.3 VCCQ/2 - 50mV VREF - 0.04 VREF + 0.15 -0.3 VTT + 0.76 -- Max 2.7 2.7 VCCQ/2 + 50mV VREF + 0.04 VCCQ + 0.3 VREF - 0.15 -- VTT - 0.76 Unit V V V V V V V V
CAPACITANCE
TA = 25C, f = 1MHz, VCC = 2.5 0.2V, VREF =1.4V 200mV Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#, CAS#, WE#) Input Capacitance (CKE0) Input Capacitance (CK0,CK0#) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 29 29 29 29 29 8 29 8 Unit pF pF pF pF pF pF pF pF
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IDD SPECIFICATIONS AND TEST CONDITIONS
0C TA 70C, VCC = 2.5V 0.2V DDR SDRAM Component Values Only DDR333 @CL=2.5 Max
W3EG6432S-D4
PRELIMINARY
Parameter
Symbol Conditions One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power- down mode; tCK=tCK(MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. Vin = Vref for DQ, DQS and DM. One device bank active; Power-down mode; tCK(MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continous burst; One device bank active;Address and control inputs changing once per clock cycle; tCK=tCK(MIN); Iout = 0mA. Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. tRC=tRC(MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands.
DDR266 @CL=2 Max
DDR266 @CL=2.5 Max
DDR266 @CL=2 Max
DDR200 @CL=2 Max
Units
Operating Current
IDD0
1000
1000
1000
1000
1000
mA
Operating Current
IDD1
1360
1280
1280
1280
1280
mA
Precharge PowerDown Standby Current Idle Standby Current Active Power-Down Standby Current
IDD2P
32
32
32
32
32
mA
IDD2F
400
360
360
360
360
mA
IDD3P
240
200
200
200
200
mA
Active Standby Current
IDD3N
480
400
400
400
400
mA
Operating Current
IDD4R
1400
1200
1200
1200
1200
mA
Operating Current
IDD4W
1400
1200
1200
1200
1200
mA
Auto Refresh Current Self Refresh Current
IDD5 IDD6
2040 32
1880 32
1880 32
1880 32
1880 32
mA mA
Operating Current
IDD7A
3280
2800
2800
2800
2800
mA
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DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst
W3EG6432S-D4
PRELIMINARY
IDD7A : OPERATING CURRENT : FOUR BANKS
1. 2. 3. Typical Case : VCC=2.5V, T=25C Worst Case : VCC=2.7V, T=10C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
4.
4.
*
*
*
*
*
*
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3
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AC OPERATING CONDITIONS
0C TA 70C, VCC = 2.5V 0.2V 335 SYMBOL tAC tCH tCL CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHF tISF tIHS tISS tIPW tMRD -0.70 0.75 0.75 0.80 0.80 2.2 12 0.75 0.2 0.2 tCH, tCL +0.70 -0.75 0.90 0.90 1 1 2.2 15 MIN -0.70 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35 0.45 1.25 0.75 0.2 0.2 tCH, tCL +0.75 +0.60 MAX +0.70 0.55 0.55 13 13 MIN -0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 +0.75 AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time 262 MAX +0.75 0.55 0.55 13 13
W3EG6432S-D4
PRELIMINARY
263/265/202 MIN -0.75 0.45 0.45 7.5 7.5/10 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 0.75 0.2 0.2 tCH, tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 1.25 +0.75 MAX +0.75 0.55 0.55 13 13 UNITS ns tCK tCK ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns 30 16, 36 16, 36 12 12 12 12 22, 23 26 26 39, 44 39, 44 23, 27 23, 27 27 NOTES
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AC OPERATING CONDITIONS (Continued)
0C TA 70C, VCC = 2.5V 0.2V 335 SYMBOL tQH tQHS tRAS tRAP tRC tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR na tREFC tREFI tVTD tXSNR tXSRD 0 75 200 42 15 60 72 15 15 0.9 0.4 12 0.25 0 0.4 15 1 tQH - tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 MIN tHP - tQHS 0.55 70,000 40 15 60 75 15 15 0.9 0.4 15 0.25 0 0.4 15 1 tQH - tDQSQ 70.3 7.8 0.6 1.1 0.6 MAX MIN tHP - tQHS 0.75 120,000 AC CHARACTERISTICS PARAMETER DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VCC Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command 262 MAX
W3EG6432S-D4
PRELIMINARY
263/265/202 MIN tHP - tQHS 0.75 40 20 65 75 20 20 0.9 0.4 15 0.25 0 0.4 15 1 tQH - tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 120,000 MAX UNITS ns ns ns ns ns ns ns ns tCK tCK ns tCK ns tCK ns tCK ns s s ns ns tCK 22 21 21 18, 19 17 37 37 42 31, 47 NOTES 22, 23
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Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load:
W3EG6432S-D4
PRELIMINARY
VTT TT 50 Reference Point 30pF
Output (VOUT (VOUT)
4.
5.
6.
7.
8.
9. 10. 11.
12.
13.
14. 15. 16.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between VIL (ACV) and VIH (AC). The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini-mum cycle time at CL = 2 for 262, 263, and 202, CL = 2.5 for 335 and 265 with the outputs open. Enables on-chip refresh and address counters. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. This parameter is sampled. VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT (DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. For slew rates < 1 V/ns and to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For 335, slew rates must be 0.5 V/ns. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
17. The intent of the "Don't Care" state after completion of the postamble is that the DQS-driven signal should either be HIGH, LOW, or High-Z and that any signal transition within the input switching region must follow valid input requirements. If DQS transitions HIGH, above DC VIH (MIN) then it must not transition LOW, below DC VIH, prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 70.3s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 7, Derating Data Valid Window (tQH - tDQSQ), shows the derating curves for duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). 26. JEDEC specifies CK and CK# input slew rate must be 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. For 335, slew rates must be 0.5 V/ns. 28. VCC must not vary more than 4 percent if CKE is not active while any device bank is active. 29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during device bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9V maximum, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V mini-mum, whichever is more positive.
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33. The voltage levels used are derived from a mini-mum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 34. VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 35. VCC and VCCQ must track each other. 36. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 37. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 38. During initialization, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC are 0V, provided a minimum of 42 of series resistance is used between the VTT supply and the input pin. 39. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option.
W3EG6432S-D4
PRELIMINARY
40. Random addressing changing and 50 percent of data changing at every transfer. 41. Random addressing changing and 100 percent of data changing at every transfer. 42. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 43. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 44. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 45. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 46. When an input signal is HIGH or LOW, it is defined as a steady state logic high or logic low. 47. The 335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency.
December 2004 Rev. 6
10
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION FOR D4
Part Number Speed 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s CAS Latency 2.5 2 2 2.5 2 2.5 2 2 2.5 2 tRCD 3 2 3 3 2 3 2 3 3 2
W3EG6432S-D4
PRELIMINARY
tRP 3 2 3 3 2 3 2 3 3 2
Height* 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") 31.75 (1.25") 31.75 (1.25")
COMMERCIAL
W3EG6432S335D4 W3EG6432S262D4 W3EG6432S263D4 W3EG6432S265D4 W3EG6432S202D4
INDUSTRIAL
W3EG6432S335D4I W3EG6432S262D4I W3EG6432S263D4I W3EG6432S265D4I W3EG6432S202D4I
NOTE: * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant) * Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred. * Industrial temperature (-40C to 85C) options
PACKAGE DIMENSIONS FOR D4
67.56 (2.666) MAX
3.81 (0.150) MAX.
3.98 0.1 (0.157 0.004) 20 (0.787)
31.75 (1.25)
2.31 (0.091) REF.
4.19 (0.165) 1.80 (0.071) 11.40 (0.449)
47.40 (1.866)
3.98 (0.157) MIN. 1.0 0.1 (0.039 0.004)
* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)
December 2004 Rev. 6 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
256MB - 32Mx64 DDR SDRAM UNBUFFERED
W3EG6432S-D4
PRELIMINARY
Revision History Rev #
Rev 1 Rev 2 Rev 3 Rev 4 Rev 5
History
Created Datasheet Corrected mechanical drawing Corrected the side view dimension on D4 to 0.039 4.1 Added industrial temperature ordering options 5.1 Added AC specs 5.2 Added lead and RoHS note 5.2 Added industrial temperature option
Release Date
3-27-01 6-17-02 10-11-02 4-04 12-04
Status
Advanced Advanced Advanced Preliminary Preliminary
Rev 6
6.1 Updated pinout's 6.2 Added source control option notes
12-04
Preliminary
December 2004 Rev. 6
12
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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